Heh.. I think the capacitive loading of that many chips would not give reliable operation, but it should be possible to stack them one extra layer high. But some support logic (an invertor) would be needed to wire up the extra necessary address line to use them.

EDIT: From the processor's point of view, each DRAM bank can have up to 128MB of memory, so a maxed-out empeg could (in theory) have 512MB of DRAM.

Cheers