Mike, would you be willing to briefly lay out what was happening? I confess I have developed an unhealthy interest in this subject.

It basically looked like _very occasionally_ an interrupt would be missed. The IR driver was already detecting this but it was difficult to see the information when in-car (it's in /proc/empeg_ir). The driver knows that an odd number of interrupts have been missed since it is edge triggered on either edge and therefore the level should alternate between interrupts.

We've solved the problem by producing a simplified interrupt handler which just collects timings and analysing them later in a bottom half. We then recoded the interrupt handler as a FIQ[1] routine which has very low latency. The standard Linux kernel never disables FIQs (and we only do to avoid concurrency problems within the IR driver itself).

[1] FIQs are fast IRQs. The handler starts execution immediately without going through a vector and has a banked set of registers so they can work without saving the state. They must be coded in assembler to be useful.

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Mike Crowe
I may not be speaking on behalf of empeg above :-)