Well, if you have a logic probe, and perhaps a logic analyzer, then start with the signals that are easily accessible on the IDE header. Those are publicly documented in the ATA Standards (t13.org). So you can trace what's happening on the header pins, and see whether the R/W, CS0/1/2 ... etc.. signals are actually working or not. Also probe for stuck data lines.

This may be easier if you hack the kernel to hold known data patterns on the pins for longer periods than what normally happens during probiing.

And/or trace the signals backwards from the header towards the CPU. Most of them go through some LS TTL buffers, and it is possible that one of those buffer chips is not working. Tracing them back is pretty much the only option, as the schematics are not redistributable.

I believe that only RobS, Patrick, and Hugo have access to the full schematics.
I have previously reverse-engineered much of this circuitry to diagnose similar problems,
but that knowledge is not in any form I can pass directly along.

Cheers